The invention relates generally to automatic test equipment and more particularly a calibration circuit arrangement and method for use in a semiconductor tester to minimize calibration processing time in a production testing environment.
Semiconductor device manufacturing typically includes test processes at both the wafer and packaged-device levels. The testing is normally carried out by automatic test equipment (ATE) that simulates a variety of operating conditions to verify the functionality of each device.
Referring to FIG. 1, a typical semiconductor tester 10 generally includes a computer workstation 12 coupled to a databus 14 that routes signals to and from pattern generation circuitry 16, timing circuitry 18 and failure processing circuitry 20. The timing circuitry responds to programmed patterns from the pattern generator to provide precisely timed tester events. The events, in turn, activate driver/comparator circuitry 22 that interfaces to one or more devices-under-test (DUTs) 24.
As the speeds of modern semiconductors increase, the edge-placement accuracy requirements for testing the DUTs become more stringent. Edge-placement accuracy generally refers to the acceptable offset of a rising or falling signal xe2x80x9cedgexe2x80x9d with respect to another edge or reference point. Consequently, ATE manufacturers must balance cost, parallelism and accuracy, among other things, when designing ATE for widespread acceptance by semiconductor manufacturers.
Like any sophisticated measuring instrument, a semiconductor tester often requires calibration of its channels in order to maintain expected edge-placement accuracy levels. With further reference to FIG. 1, calibration circuitry 26 modifies the timing circuitry output signals, as needed during a test, to compensate for signal degradation and skews between the individual channels 28. Calibration often involves detecting channel-to-channel timing skews, and providing compensating delays to the tester signals during the test to account for the skew. This is important in order to ensure that all the signal edges applied to or captured from the DUTs on a given cycle are done so at the DUT pins synchronously.
With reference to FIG. 2, the channel architecture for a semiconductor tester typically includes a driver 28, a comparator 30, a transmission line 32 and a plurality of relays R1-R4 that selectively vary the channel signal path between the driver/comparator. The transmission line is typically open-ended during calibration procedures. Conventional calibration schemes for high performance testers often employ time-domain-reflectometry procedures, wherein each channel CH0-CHN (in phantom) of the tester is sequentially fed a calibration signal from a master driver/comparator 36. A switch matrix 38 directs the calibration signal to/from the master driver/comparator to the channels. The channel relays are then selectively activated to route the calibration signal and its reflection appropriately. By measuring the delay between the application of the pulse and its reflection, calibration offsets may be calculated, stored in a calibration memory associated with the calibration circuitry 26 (FIG. 1), and applied to the tester signals during a test to minimize channel-to-channel skew.
While this method works well for its intended applications, the sequential measurement scheme takes a substantial amount of time. The longer a tester remains out of a production line (to undergo calibration) the costlier the test process overall. Thus, to desirably reduce test costs, it would be beneficial to reduce calibration times while still retaining the required level of accuracy. The apparatus and method of the present invention addresses these needs.
The ring calibration apparatus and method of the present invention provides for high-speed calibration of multiple tester channels in parallel. As a result, semiconductor device manufacturers can minimize tester downtime in order to maximize device throughput, and correspondingly reduce test costs.
To realize the foregoing advantages, the invention in one form comprises a calibration circuit for use in automatic test equipment. The calibration circuit includes a calibration signal driver having an output and a closed-loop transmission line coupled to the output of the calibration signal driver. A plurality of comparators having respective reference inputs, test signal inputs, and calibration inputs are coupled to the closed-loop transmission line. The plurality of comparators are adapted to selectively receive calibration signals generated by the driver in parallel along the closed-loop transmission line.
In another form, the invention comprises a calibration system for use with automatic test equipment. The calibration system includes a region card including a master driver having an output, and a master ring transmission line coupled to the driver output. The system further includes a plurality of channel cards, each channel card including a calibration circuit. The calibration circuit includes a calibration signal driver having an output and a closed-loop transmission line coupled to the output of the calibration signal driver. A plurality of comparators are included, each comparator having a reference input, a test signal input, and a calibration input. The calibration input is coupled to the closed-loop transmission line. The plurality of comparators are adapted to selectively receive calibration signals generated by the driver in parallel along the closed-loop transmission line, and wherein the calibration signal drivers are coupled to the master ring transmission line.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.